HPM6700/6400 Series

The HPM6700/6400 series microcontrollers are equipped with three 12 bit and one 16 bit ADC controller, the HPM6300 and HPM6200 series microcontrollers are equipped with three 16 bit ADC controllers, and the HPM5300 series microcontroller is equipped with two 16 bit controllers. The 12 bit ADC supports a maximum sampling rate of 5MSPS, while the 16 bit ADC supports a maximum sampling rate of 2MSPS. These ADC supports multiple sampling modes such as read, cycle, sequence, and preemption. The input mode supports single ended input(12 bit, 16 bit) and differential input (12 bit), and supports configurable resolution and number of sampling cycles, as well as using internal DMA to write conversion results into memory.

Hpm_motor is a library file for core algorithms of motor control, which aims to continuously update and improve specific functional algorithms through modular management; For users, there is no need to worry about how the underlying implementation is implemented, which accelerates the development of user programs. Trajectory planning algorithm: When the motor starts and stops, there is a step change in speed. Sudden changes in motor speed may lead to current overload. So, acceleration and deceleration control algorithms are usually used to plan motor speed. The trajectory planning algorithm used in libhpm_motor. a is an S-shaped curve, whose core function is to control the change of acceleration by varying the magnitude of acceleration, ensuring that the acceleration does not suddenly change, making the acceleration and deceleration speed curves smooth, thereby achieving the goal of smooth operation of the motor

For LED large screen display applications, the high-performance HPM6750 can perfectly solve high-speed link design through a dual gigabit Ethernet transparent transmission solution. The HPM6750 supports 2 Ethernet controllers(ENET), which comply with standard Ethernet MAC, and support 10/100/1000Mbps data transfer rate.It also supports PHY in RMII and RGMII modes. The ENET Ethernet controller has its own DMA, so the CPU load for data reception and transmission is zero. The HPM6750 transmits Ethernet data received by two PHY through an Ethernet controller, with a transmission rate of 780Mb/s. In applications that require extremely high real-time control , the LED large screen display scheme based on high-performance HPM6750 is not inferior to FPGA scheme, not only with lower cost but also further reducing development difficulty.

This solution outlines the method for driving an 8080 display using the FEMC (Flexible External Memory Controller). By interfacing the 8080 display with the FEMC controller, similar to accessing RAM operations, the 8080 display can be easily powered on and illuminated through reading and writing to corresponding addresses, achieving high refresh rates. The HPM6700/6400, and 6300 series microcontrollers are equipped with a versatile FEMC controller for external memory. A comparison between the timing diagrams of the 8080 protocol and SRAM reveals that the parallel port timing of 8080 is essentially identical to that of SRAM. As a result, the FEMC controller can be leveraged to drive 8080 displays.

This plan mainly introduces how to use the built-in SEC_IMG-OFFSET function of bootrom for OTA upgrade. We use UART xmodem function for OTA upgrade and run encrypted firmware.

This solution is a customized Level 2 Boot upgrade solution that supports firmware upgrades in both Level 2 Boot and APP applications. Support upgrade package creation and support different verification algorithms, such as checksum/xor/crc32/sha1/sha256/sm3; Support ping/pang upgrade, second level Boot supports remap jump, user-app only requires one project and linker file; Level 2 Boot supports version verification and intelligent redirection.

This scheme triggers ADC sampling at a specific PWM moment, and at the same time triggers HDMA to operate SPI controller at another specific PWM point. It relies on HDMA chain mode to create a circular linked list, and HDMA automatically completes SPI read and write tasks, storing the read data in the designated memory without CPU involvement. At the same time, the HPM ADC controller also has its own DMA, which stores the sampled data in the designated memory after ADC sampling is completed, and the CPU does not need to participate. Users can directly use the ADC sampling results and SPI encoder information in the ADC sampling completion interrupt to perform subsequent closed-loop algorithms and ultimately adjust the PWM duty cycle for the next cycle.

The HPM Power solution summarizes the requirements of power management MCU, integrates them into a universal software architecture solution, and provides various API interfaces. The HPM Power Driver API is a driver API interface for power supplies based on the HPM Software Development Kit (HPM SDK) package. The Power API abstracts hardware components such as PWM pairs, PWM, and ADC channels into custom ID numbers, and upper layer applications only need to focus on the abstract ID numbers.

This scheme takes the HPM6300 development board as an example to introduce the application of performing2MSPS sampling rate for 16 bit ADC sampling and sending the sampled data to the host computer through ENET LWIP TCP. ADC sampling uses preemption conversion mode and is triggered by PWM, with ENET LWIP TCP sending 1024 16 bit sampled data each time. This scheme triggers ADC sampling and HDMA conversion of ADC data at specific time points through PWM, and relies on HDMA chain mode to create a circular linked list. Considering that interrupt response occupies CPU resources, a state identifier is added in the chain task to not enable interrupts, thus achieving fully automatic completion of ADC sampling and data conversion without CPU involvement. The converted data is then placed in ILM/DLM, and the CPU has zero waiting access. Ultimately achieving optimal performance.

The HPM6750EVK2 provides interfaces for most of the peripherals of the HPM6750 microcontroller, including display and camera interfaces, 1 SD card slot, 2 USB Type-C ports, one Gigabit Ethernet port, one 100 Megabit Ethernet port, CAN FD interface, audio interface, and more. It also expands with NOR Flash, SDRAM, and other external memory. Dimensions: 146 x 102 mm.

Package: BGA289

Package: BGA196

Package: BGA196

Package: BGA289

Package: BGA196

Package: BGA289

Package: BGA289

Package: BGA289