HPM5E00 Series

Performance

- RISC-V core supports double-precision floating-point arithmetic and powerful DSP extensions with a maximum operating frequency of 480 MHz, delivering 2,712 CoreMark™ and 1,368 DMIPS of computing performance. 

- Equipped with 32 KB unified instruction/data cache (I/D Cache), a total of up to 256 KB zero-wait local instruction and data memory (ILM/DLM), and an additional 256 KB general-purpose SRAM. This architecture effectively eliminates performance degradation caused by low-speed external memory access.

Real-Time Ethernet Subsystem

- EtherCAT slave controller supporting up to 3 ports- 1000 Mbps Ethernet MAC controller 

- Two integrated 100 Mbps Ethernet PHYs

Enhanced Motion Control Subsystem

- Two 8-channel enhanced PWM controllers with modulation resolution as high as 100 ps 

- Motion sensor interfaces, including interfaces for incremental position sensors and magnetic encoders

- Pulse-type position output interface- Programmable Logic Block (PLB)

Memory & Memory Interfaces

- On-chip 1 MB Flash memory 

- Programmable external parallel expansion bus supporting various external devices including FPGAs

Power Management System

- Integrated high-efficiency DC-DC converters and LDO regulators enable single-supply system power input. Dynamic output voltage adjustment balances performance and power consumption, combining excellent flexibility, usability and power efficiency. 

- Multi-power-domain design supports multiple configurable low-power modes. 

- Ultra-low-power standby mode

Comprehensive Peripherals

- Versatile communication interfaces: 1 high-speed USB controller with integrated PHY, up to 4 CAN/CAN-FD controllers, plus abundant UART, SPI and I2C peripherals. 

- Sigma-Delta digital filter module (SDM) embedded with SINC digital filters, compatible with external sigma-delta modulators. 

- Two 16-bit high-precision ADCs with a sampling rate of 2 MSPS; the conversion rate can reach 4 MSPS when operating in 12-bit mode, with up to 16 analog input channels, alongside two analog comparators.

- Up to 20 32-bit timers and 3 watchdog timers

Security

- Chip lifecycle-based security management and multi-type attack detection to further protect confidential sensitive data. 

- Embedded Boot ROM enables secure firmware download and upgrade via USB or UART interfaces.

Terminology Specification

- DC-DC, PHY, MAC, FPGA, CoreMark™, DMIPS: Industry standard proper nouns retain original capitalization. 

- ILM/DLM/PLB/SDM: Standard abbreviations for MCU internal modules widely used in datasheets. 

- Sigma-Delta: Standard written form for Σ∆ in English technical documents. 

- EtherCAT slave controller: Fixed industrial terminology for EtherCAT slave side IP core. 

- Boot ROM / secure firmware upgrade: Standard secure boot terminology for industrial MCUs.